The present invention relates to a micro controller. More particularly, the present invention relates to a micro controller for updating an internal algorithm which controls operation of a system and a method of updating the same.
Recently, efforts for enhancing operation characteristics of mobile devices such as a camcorder, a digital camera, a portable phone, an MP3 (MPEG-1 Layer3) player, etc. have been performed as the demand for mobile devices has increased. Specifically, since the mobile device should operate at low power for a long time, many low power consumption type mobile devices have been developed.
To reduce power consumption of the mobile device, power consumption of semiconductor chips included in the mobile device should be decreased. The mobile device has a micro controller for controlling operation of its elements.
The micro controller executes internal operation processes, e.g. arithmetic operations, Boolean operations, etc., and generates a control signal synchronized with a clock signal. The control signal controls timing of a system and operation of elements in the system.
FIG. 1 is a block diagram illustrating a common micro controller.
In FIG. 1, a micro controller 130 is connected to a command interface circuit 110 for processing a command inputted from an external device and an oscillator 120 for generation of a clock. The micro controller 130 includes a clock generating circuit 131 for receiving two clocks CLOCK1 and CLOCK2 from the oscillator 120 and for generating a clock needed for its operation, a storing circuit 132 for storing algorithm program information for command operation, a program counter 133 for performing an address count so as to execute a command of the storing circuit 132, a command decoder 134 for decoding the command stored in the storing circuit 132, a flag processing circuit 135 for processing flag information provided from the command decoder 134 and for providing the flag information to the clock generating circuit 131 so that the clock is generated, and an output controller 136 for outputting a control command provided from the storing circuit 132 or the command decoder 134 for operation of the memory device.
The micro controller 130 drives the algorithm program stored in the storing circuit 132 in response to the operation command inputted through the command interface circuit 110. The algorithm program is provided in sequence to the command decoder 134, the flag processing circuit 135 or the output controller 136 through a bus M_BUS<i-1:0> by changing the address of the storing circuit 132 through the program counter 133.
The flag processing circuit 135 controls the clock generating circuit 131 in response to the flag information provided from the command decoder 134 or the storing circuit 132 so that the clock generating circuit 131 generates the operation clock and provides the generated operation clock to the storing circuit 132.
The command decoder 134 decodes the command transmitted from the storing circuit 132, and provides the decoded command to the flag processing circuit 135 or the output controller 136.
The output controller 136 outputs control signals provided from the storing circuit 132 or the command decoder 134 to an external device.
The algorithm program for operation control of the memory device is stored in the storing circuit 132, e.g. a read only memory (ROM). However, it is difficult for the storing circuit 132 to change or upgrade the algorithm program in accordance with characteristics of the ROM.